A design and implementation of CATV STB using VHDL

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A source generation scheme of CATV STB designed and implemented by VHDL Abstract: This paper introduces a source generation scheme of CATV STB. The scheme uses programmable logic devices to complete the format conversion of computer EISA bus output data, so as to improve the data output rate and meet the requirements of information sources. Moreover, the scheme adopts an open structure and can be extended by software modification. The function design process of programmable logic devices using VHDL is also described in detail

key words: CATV set top box VHDL language data format conversion programmable logic device (PLD)

vhdl is a hardware description language developed with the development of PLD. It is a part of the VHSIC (ultra high speed integrated circuit) program of the Ministry of defense of the United States of America, which cleared the value of digital display in 1980, and became the industrial standard of the Ministry of defense and IEEE in 1986 and 1987 respectively. As a standard language used in hardware design, VHDL has strong description ability and can support three different levels of design: system behavior level, register transfer level and gate level. In this way, designers can easily use the same language in the whole process of top-down design. Moreover, VHDL design is a concept driven high-level design technology. Designers do not need to describe the circuit through the gate level schematic diagram, but describe the function of the target. Because they get rid of the constraints of circuit details, designers can concentrate on the design scheme and conception. Therefore, the design work saves time and effort, speeds up the design cycle, and the process conversion becomes easy. VHDL design technology plays a very important role in the development of programmable application specific integrated circuits (ASIC)

since Microsoft put forward the Venus plan, set-top box has become the main target pursued by the information industry and the mainstream product in information appliances. All countries are stepping up the development of set-top boxes. China has also put forward the corresponding Nu Wa plan. Many scientific research institutions and manufacturers across the country are carrying out research in this regard. As China is rich in cable TV Resources and has a great market prospect, the research on cable TV set-top box is particularly eye-catching. However, digital TV service has not been fully developed in China, so it is not easy to find a suitable signal source in the debugging process of set-top box, and it has to be realized by outputting standard video code stream through computer. But the data rate of EISA bus parallel output of most computers is difficult to meet the needs of practical work. Although EISA bus can output 16 bit parallel data at a time, it still needs a conversion process for devices that can only process 8-bit parallel data at a time. This paper introduces a design scheme of data format conversion. In this scheme, VHDL is used to program a CPLD chip to realize the conversion from 16 bit parallel data to 8-bit parallel data, and the data output rate of EISA port is doubled to meet the source requirements

1 characteristics of VHDL

vhdl is a design oriented, multi-level, multi domain and unanimously recognized, standard hardware description language. It has the following characteristics:

it can formally and abstractly represent the structure and behavior of the circuit, reducing the difficulty of hardware circuit design

the top-down design method is adopted to support the description of hierarchy and domain in logical design; It supports three levels of Description: behavior description, RTL mode description, and gate level description (logic synthesis)

early simulation of the system can be carried out to ensure the correctness of the design

the main design files are source programs written in VHDL language, which is convenient for document management

the hardware description is independent of the implementation process

since VHDL has been regarded as an IEEE industrial standard, its language standard, specification and syntax are relatively strict and easy to share and reuse. Moreover, VHDL has complete design technology, flexible methods and wide support. At present, most EDA tools almost support VHDL language to varying degrees

2cpld external pin description

the chip used in this scheme is Xilinx's CPLD 9500 series chip, and its type is xc95108-7 PC8 recycled resin composite inspection manhole cover cj/t 121 ⑵ 0004. The chip has a total of 84 external pins, of which 5 pins are grounded, 6 pins are connected to the power supply, 4 pins are used for JTAG, and the remaining pins are I/O pins. According to the signal characteristics of EISA bus and the requirements of information source, the external pins used by the chip are as shown in Figure 1

input signal in Figure 1:

data in15 ~ 0 input data signal

address15 ~ 0 input address signal

reset reset signal

aen address permission signal

clk input clock signal

iowi/O write signal

output signal:

io cs16 bit I/O chip selection signal

data out7 ~ 0 exported Data signal

den output data enable signal

dclk output data clock signal

3 overall system design

after the system is started, the host sends an address signal to the I/O port. When AEN is at low level, the system decodes the address. After successful decoding, an enable signal is generated to open the data temporary storage unit. After the data arrives, the data temporary storage unit locks the 16 bit parallel data on the bus into the temporary storage, and generates an allow signal permit to allow data format conversion. Next, the system selects the output according to the current state, completes the format conversion, and generates the corresponding output data enable signal den and output data clock signal DCLK. After the whole process, reset each signal to start a new conversion cycle. Therefore, the whole system should include five logic parts: address decoding, data temporary storage, state control, reset control and conversion output

3.1 overall block diagram of the system

the overall block diagram of the system is shown in Figure 2

3.2 the working sequence of the system

the sequence of the conversion process is shown in Figure 3

4 VHDL language description

4.1 description of each unit module

address decoding unit

the correct communication between computer and I/O equipment is completed through the addressing operation of I/O space. Each I/O port is assigned an address. In this scheme, the address of the port is set to 0280h, and the full decoding method is adopted. At the same time, in order to avoid DMA operation control bus, AEN is also involved in decoding and controlled by clock signal. After successful decoding, an enable signal is generated (high level is valid), and IO_ CS signal pulled low

When the

data temporary storage unit

enable signal is invalid, the data temporary storage unit is in the high resistance state. After both the signal and the write signal Iow (active at low level) become active, the data on the bus will be read into the data temporary storage unit at the falling edge of the next clock (ensuring that the data is valid during sampling), and an allow signal permit will be generated to allow the system to perform format conversion

status control unit

this is the control part of the system. The control of the system state is realized by the system control signals simbol and sign driven by the clock signal. Every time the system completes the output of 8-bit data, the state changes on the falling edge of the same clock, and another control signal varb (active at low level) is generated. After reset, the system returns to the initial state. The state change process is as follows:

conversion output unit

conversion output unit is the core of the system. It includes three parts: data format conversion, data enable signal den output, and data clock signal DCLK output. The conversion output of data is determined by the current state of the system. After the permit signal is valid, the output unit is converted to detect the system status at the rising edge of the clock: when the status is first, the high 8 bits are output; When the status is second, the lower 8 bits are output; When the status is third, the system resets to complete one conversion and start the next conversion cycle. In the process of conversion, the system controls the signals simbol and sign (active at low level) at the same time

the output data enable signal den is generated according to the MPEG-2 standard code stream format and is used for data signal synchronization. In MPEG-2 standard, the code stream is transmitted in the form of packets. Each packet has a unified packet identifier PID, whose hexadecimal form is 47h. From the first byte (47h) in the packet, den becomes valid (high level) and remains until the 188th byte. Den remains low for the next 16 bytes

the output data clock signal DCLK is used as the sampling clock of the demultiplexing unit. It is generated by the control signals sign, permit and the current state control of the system. In order to keep the data valid during sampling, the output of DCLK is half a machine cycle later than the corresponding output data

After the

reset control unit

conversion, the system needs to be reset to ensure the smooth progress of the next conversion. The generation of reset signal depends on three control quantities: the current state of the system is third, the control signal varb is low level, and the control signal simbol is high level. After reset, the output terminal is in high resistance state, and other signals are invalid values. The system returns to the initial state

4.2 door level description of the system

the VHDL description process of the whole system is shown in Figure 4

in a word, the source generation scheme of STB is an important subject in the process of STB debugging. The solution proposed in this paper is simple, practical and easy to implement, which has been proved to be feasible by practice. At the same time, the VHDL design method is adopted in the hardware implementation, which also provides great flexibility for the whole scheme. If the traditional method is adopted to realize the scheme, the general logic devices must be selected first, and then the circuit design shall be carried out to complete each independent functional module, and then the functional modules shall be connected to complete the hardware design of the whole circuit. Finally, the simulation and debugging can be carried out until the completion of the whole system. Such a process often takes a long time and is time-consuming and laborious, especially for a large project. Using high-level design technologies such as VHDL, designers only need to concentrate on the design scheme and conception. After the successful description and compilation, the software simulation and debugging can be carried out directly after the system integration. The completion cycle of the whole system is greatly shortened, and VHDL has nothing to do with the process. It does not limit the simulation tools and design methods, thus giving designers a free choice

with the increasing improvement and perfection of electronic technology, ISP (system programmable) function provides PLD with higher flexibility, which enables PLD to develop towards high-density and large-scale to meet the requirements of complex systems, so that the design of programmable ASIC is gradually transferred to the design of high-temperature resistant and high-strength special engineering plastic layer, which is the earliest one. As an important high-level design technology, VHDL has also become a method that contemporary electronic designers must master when designing digital hardware


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